VHDL Archives - Engineers Garage https://www.engineersgarage.com/tutorials/vhdl-tutorials/ Electronic Projects, Electrical Engineering Resources, Makers Articles and Product News Wed, 22 May 2024 11:06:34 +0000 en-US hourly 1 https://www.engineersgarage.com/wp-content/uploads/2019/08/cropped-eg-favicon-32x32.png VHDL Archives - Engineers Garage https://www.engineersgarage.com/tutorials/vhdl-tutorials/ 32 32 VHDL Tutorial – 5: Design, simulate and verify NAND, NOR, XOR and XNOR gates using AND-OR-NOT gates in VHDL https://www.engineersgarage.com/vhdl-tutorial-5-design-simulate-and-verify-nand-nor-xor-and-xnor-gates-using-and-or-not-gates-in-vhdl/ https://www.engineersgarage.com/vhdl-tutorial-5-design-simulate-and-verify-nand-nor-xor-and-xnor-gates-using-and-or-not-gates-in-vhdl/#respond Wed, 22 May 2024 00:33:37 +0000 https://www.engineersgarage.com/?p=61726 In the previous VHDL tutorial 4, we designed and simulated all seven logic gates (AND, OR, NOT, NAND, NOR, XOR, and XNOR) in VHDL. (If you are not following this VHDL tutorial series one by one, please go through all previous tutorials of these series before going ahead in this tutorial) In this tutorial, We…

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]]> https://www.engineersgarage.com/vhdl-tutorial-5-design-simulate-and-verify-nand-nor-xor-and-xnor-gates-using-and-or-not-gates-in-vhdl/feed/ 0 VHDL Tutorial 6: Design and verify De Morgan’s Theorem using VHDL https://www.engineersgarage.com/vhdl-tutorial-6-design-and-verify-de-morgans-theorem-using-vhdl/ https://www.engineersgarage.com/vhdl-tutorial-6-design-and-verify-de-morgans-theorem-using-vhdl/#respond Wed, 22 May 2024 00:32:00 +0000 https://www.engineersgarage.com/?p=61739 In previous tutorial VHDL tutorial 5, we built NAND, NOR, XOR, and XNOR gates using AND-OR-NOT gates in VHDL. (If you are not following this VHDL tutorial series one by one, please go through all previous tutorials of these series before going ahead in this tutorial) In this tutorial, We shall write a VHDL program…

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]]> https://www.engineersgarage.com/vhdl-tutorial-6-design-and-verify-de-morgans-theorem-using-vhdl/feed/ 0 VHDL Tutorial – 7 NAND gate as universal gate using VHDL https://www.engineersgarage.com/vhdl-tutorial-7-nand-gate-as-universal-gate-using-vhdl/ https://www.engineersgarage.com/vhdl-tutorial-7-nand-gate-as-universal-gate-using-vhdl/#respond Wed, 22 May 2024 00:31:34 +0000 https://www.engineersgarage.com/?p=61838 In previous tutorials VHDL tutorial (#6), we built a circuit for D Morgan’s Theorems in VHDL and verified its output to prove D Morgan’s theorems. (If you are not following this VHDL tutorial series one by one, you are requested to go through all previous tutorials of these series before going ahead in this tutorial)…

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]]> https://www.engineersgarage.com/vhdl-tutorial-7-nand-gate-as-universal-gate-using-vhdl/feed/ 0 VHDL Tutorial – 8: NOR gate as a universal gate https://www.engineersgarage.com/vhdl-tutorial-8-nor-gate-as-a-universal-gate/ https://www.engineersgarage.com/vhdl-tutorial-8-nor-gate-as-a-universal-gate/#respond Tue, 21 May 2024 12:30:57 +0000 https://www.engineersgarage.com/?p=61983 Note: it’s recommended to follow this VHDL tutorial series in order, starting with the first tutorial. In the previous tutorial, VHDL Tutorial – 7, we learned how to build different gates (such as AND, OR, NOR, NOT, etc.) by using the NAND gate in VHDL — proving that the NAND gate is universal. In this…

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]]> https://www.engineersgarage.com/vhdl-tutorial-8-nor-gate-as-a-universal-gate/feed/ 0 VHDL Tutorial – 9: Digital circuit design with a given Boolean equation https://www.engineersgarage.com/vhdl-tutorial-9-digital-circuit-design-with-a-given-boolean-equation/ https://www.engineersgarage.com/vhdl-tutorial-9-digital-circuit-design-with-a-given-boolean-equation/#respond Tue, 21 May 2024 12:29:03 +0000 https://www.engineersgarage.com/?p=62011 Note: it’s recommended to follow this VHDL tutorial series in order, starting with the first tutorial. In previous tutorials VHDL tutorial – 8, we learned how to build different gates (such as AND, OR, NOR, NOT, etc.) by only using the NOR gate in VHDL. We were able to successfully prove that he NOR gate is…

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]]> https://www.engineersgarage.com/vhdl-tutorial-9-digital-circuit-design-with-a-given-boolean-equation/feed/ 0 VHDL Tutorial – 10: Designing half and full-adder circuits https://www.engineersgarage.com/vhdl-tutorial-10-designing-half-and-full-adder-circuits/ https://www.engineersgarage.com/vhdl-tutorial-10-designing-half-and-full-adder-circuits/#respond Tue, 21 May 2024 12:28:42 +0000 https://www.engineersgarage.com/?p=62028 Note: it’s recommended to follow this VHDL tutorial series in order, starting with the first tutorial. In the previous tutorial VHDL Tutorial – 9, we learned how to build digital circuits from given Boolean equations.  In this tutorial, we will: Write a VHDL program to build half and full-adder circuits.   Verify the output waveform of the…

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]]> https://www.engineersgarage.com/vhdl-tutorial-10-designing-half-and-full-adder-circuits/feed/ 0 VHDL tutorial 13: Design 3×8 decoder and 8×3 encoder using VHDL https://www.engineersgarage.com/vhdl-tutorial-13-design-3x8-decoder-and-8x3-encoder-using-vhdl/ https://www.engineersgarage.com/vhdl-tutorial-13-design-3x8-decoder-and-8x3-encoder-using-vhdl/#respond Mon, 16 Oct 2023 17:35:51 +0000 https://www.engineersgarage.com/?p=62411 In the previous tutorial VHDL tutorial, we designed an 8-bit parity generator and 8-bit parity checker circuits using VHDL. (If you are not following this VHDL tutorial series one by one, you are requested to go through all previous tutorials of these series before going ahead in this tutorial) In this tutorial, We shall write…

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]]> https://www.engineersgarage.com/vhdl-tutorial-13-design-3x8-decoder-and-8x3-encoder-using-vhdl/feed/ 0 VHDL Tutorial 14: Design 1×8  demultiplexer and 8×1 multiplexer using VHDL https://www.engineersgarage.com/vhdl-tutorial-14-design-1x8-demultiplexer-and-8x1-multiplexer-using-vhdl/ https://www.engineersgarage.com/vhdl-tutorial-14-design-1x8-demultiplexer-and-8x1-multiplexer-using-vhdl/#respond Mon, 16 Oct 2023 17:34:19 +0000 https://www.engineersgarage.com/?p=62427 In the previous tutorial VHDL tutorial, we designed 8×3 encoder and 3×8 decoder circuits using VHDL. (If you are not following this VHDL tutorial series one by one, you are requested to go through all previous tutorials of these series before going ahead in this tutorial) In this tutorial, We shall write a VHDL program…

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]]> https://www.engineersgarage.com/vhdl-tutorial-14-design-1x8-demultiplexer-and-8x1-multiplexer-using-vhdl/feed/ 0 VHDL Tutorial 15: Design a clocked SR latch (flip-flop) using VHDL https://www.engineersgarage.com/vhdl-tutorial-15-design-clocked-sr-latch-flip-flop-using-vhdl/ https://www.engineersgarage.com/vhdl-tutorial-15-design-clocked-sr-latch-flip-flop-using-vhdl/#respond Mon, 16 Oct 2023 17:33:23 +0000 https://www.engineersgarage.com/?p=62506 Note: it’s recommended to follow this VHDL tutorial series in order, starting with the first tutorial. In the previous tutorial, VHDL tutorial – 14, we designed two circuits using VHDL: a 1×8 de-multiplexer and a 8×1 multiplexer. In this project, we will, Write a VHDL program to build a clocked SR Latch (flip-flop) circuit Verify the…

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]]> https://www.engineersgarage.com/vhdl-tutorial-15-design-clocked-sr-latch-flip-flop-using-vhdl/feed/ 0 VHDL Tutorial 16: Design a D flip-flop using VHDL https://www.engineersgarage.com/vhdl-tutorial-16-design-a-d-flip-flop-using-vhdl/ https://www.engineersgarage.com/vhdl-tutorial-16-design-a-d-flip-flop-using-vhdl/#respond Mon, 16 Oct 2023 17:32:47 +0000 https://www.engineersgarage.com/?p=62579 Note: it’s recommended to follow this VHDL tutorial series in order, starting with the first tutorial. In the previous tutorial, we designed a clocked SR latch circuits using VHDL (which is a very high-speed integrated circuit hardware description language). For this project, we will: Write a VHDL program to build a D flip-flop circuit Verify the…

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]]> https://www.engineersgarage.com/vhdl-tutorial-16-design-a-d-flip-flop-using-vhdl/feed/ 0 VHDL Tutorial 17: Design a JK flip-flop (with preset and clear) using VHDL https://www.engineersgarage.com/vhdl-tutorial-17-design-a-jk-flip-flop-with-preset-and-clear-using-vhdl/ https://www.engineersgarage.com/vhdl-tutorial-17-design-a-jk-flip-flop-with-preset-and-clear-using-vhdl/#respond Mon, 16 Oct 2023 17:31:05 +0000 https://www.engineersgarage.com/?p=62598 Note: it’s recommended to follow this VHDL tutorial series in order, starting with the first tutorial. In the previous tutorial – VHDL tutorial 16 – we designed a D flip-flop circuit by using VHDL. For this project, we will: Write a VHDL program to build a JK flip-flop circuit Verify the output waveform of the program…

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]]> https://www.engineersgarage.com/vhdl-tutorial-17-design-a-jk-flip-flop-with-preset-and-clear-using-vhdl/feed/ 0 VHDL Tutorial 18: Design a T flip-flop (with enable and an active high reset input) using VHDL https://www.engineersgarage.com/vhdl-tutorial-18-design-a-t-flip-flop-with-enable-and-an-active-high-reset-input-using-vhdl/ https://www.engineersgarage.com/vhdl-tutorial-18-design-a-t-flip-flop-with-enable-and-an-active-high-reset-input-using-vhdl/#respond Mon, 16 Oct 2023 17:30:05 +0000 https://www.engineersgarage.com/?p=62610 Note: it’s recommended to follow this VHDL tutorial series in order, starting with the first tutorial. In the previous tutorial, VHDL tutorial – 17, we designed a JK flip-flop circuit by using VHDL. For this project, we will: Write a VHDL program to build the T flip-flop circuit Verify the output waveform of the program (the…

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]]> https://www.engineersgarage.com/vhdl-tutorial-18-design-a-t-flip-flop-with-enable-and-an-active-high-reset-input-using-vhdl/feed/ 0 VHDL Tutorial 1: Introduction to VHDL https://www.engineersgarage.com/vhdl-tutorial-1-introduction-to-vhdl/ https://www.engineersgarage.com/vhdl-tutorial-1-introduction-to-vhdl/#respond Mon, 19 Dec 2022 01:37:34 +0000 https://www.engineersgarage.com/?p=61330 What is VHDL? VHDL is a short form of VHSlC Hardware Description Language where VHSIC stands for Very High Speed Integrated Circuits It’s a hardware description language – means it describes the behavior of a digital circuit, and also it can be used to derive or implement a digital circuit/system hardware It can be used…

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]]> https://www.engineersgarage.com/vhdl-tutorial-1-introduction-to-vhdl/feed/ 0 VHDL Tutorial 2: VHDL programs https://www.engineersgarage.com/vhdl-tutorial-2-vhdl-programs/ https://www.engineersgarage.com/vhdl-tutorial-2-vhdl-programs/#respond Mon, 19 Dec 2022 01:36:17 +0000 https://www.engineersgarage.com/?p=61387 In the previous tutorial on the basics of VHSlC Hardware Description Language or VHDL, we discussed the VHDL design flow and program structure. Now, it’s time to learn about the VHDL programs. However, please note, the prerequisite for VHDL programming are the fundamentals of digital electronics and digital circuit design. To fully understand these programs,…

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]]> https://www.engineersgarage.com/vhdl-tutorial-2-vhdl-programs/feed/ 0 VHDL Tutorial 3: Using MAX+II to compile, simulate & verify a VHDL program https://www.engineersgarage.com/vhdl-tutorial-3-using-maxii-to-compile-simulate-verify-a-vhdl-program/ https://www.engineersgarage.com/vhdl-tutorial-3-using-maxii-to-compile-simulate-verify-a-vhdl-program/#respond Mon, 19 Dec 2022 01:35:08 +0000 https://www.engineersgarage.com/?p=61388 In the previous two tutorials, we learned about VHDL basics and programs. Next, we’ll simulate and verify the VHDL programs.  To edit, compile, execute (simulate), or verify a VHDL program, there are requirements including software tools, such as: ISE from XILINX ModelSim from Mentor Graphics Riviera from Aldec Quartus-II from Altera etc.  All of these…

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]]> https://www.engineersgarage.com/vhdl-tutorial-3-using-maxii-to-compile-simulate-verify-a-vhdl-program/feed/ 0 VHDL Tutorial – 4: design, simulate and verify all digital GATE (AND, OR, NOT, NAND, NOR, XOR & XNOR) in VHDL https://www.engineersgarage.com/vhdl-tutorial-4-design-simulate-and-verify-all-digital-gate-and-or-not-nand-nor-xor-xnor-in-vhdl/ https://www.engineersgarage.com/vhdl-tutorial-4-design-simulate-and-verify-all-digital-gate-and-or-not-nand-nor-xor-xnor-in-vhdl/#respond Mon, 19 Dec 2022 01:34:51 +0000 https://www.engineersgarage.com/?p=61721 In previous tutorial VHDL tutorial  3, we have learned how to design, simulate, and verify any digital circuit in VHDL using Altera’s MAX+II VHDL simulator software. (If you are not following this VHDL tutorial series one by one, you are requested to go through all previous tutorials of these series before going ahead in this…

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]]> https://www.engineersgarage.com/vhdl-tutorial-4-design-simulate-and-verify-all-digital-gate-and-or-not-nand-nor-xor-xnor-in-vhdl/feed/ 0 VHDL Tutorial – 19: Designing a 4-bit binary counter using VHDL https://www.engineersgarage.com/vhdl-tutorial-19-designing-a-4-bit-binary-counter-using-vhdl/ https://www.engineersgarage.com/vhdl-tutorial-19-designing-a-4-bit-binary-counter-using-vhdl/#respond Mon, 24 May 2021 21:01:43 +0000 https://www.engineersgarage.com/?p=62669 Note: it’s recommended to follow this VHDL tutorial series in order, starting with the first tutorial. In the previous tutorial, VHDL – 18, we designed a T-flip flop using VHDL. For this project, we will: Write a VHDL program a VHDL program to build a 4-bit binary counter Verify the output waveform of the program (the…

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]]> https://www.engineersgarage.com/vhdl-tutorial-19-designing-a-4-bit-binary-counter-using-vhdl/feed/ 0 VHDL Tutorial – 20: Designing 4-bit binary-to-gray & gray-to-binary code converters https://www.engineersgarage.com/vhdl-tutorial-20-designing-4-bit-binary-to-gray-gray-to-binary-code-converters/ https://www.engineersgarage.com/vhdl-tutorial-20-designing-4-bit-binary-to-gray-gray-to-binary-code-converters/#respond Mon, 24 May 2021 21:00:30 +0000 https://www.engineersgarage.com/?p=62788 Note: it’s recommended to follow this VHDL tutorial series in order, starting with the first tutorial. In the previous tutorial, VHDL Tutorial – 19, we designed a 4-bit binary counter using VHDL. In this tutorial, we will: Write a VHDL program to build a 4-bit binary to gray, and gray to the binary code converter Verify…

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]]> https://www.engineersgarage.com/vhdl-tutorial-20-designing-4-bit-binary-to-gray-gray-to-binary-code-converters/feed/ 0 VHDL Tutorial – 12: Designing an 8-bit parity generator and checker circuits https://www.engineersgarage.com/vhdl-tutorial-12-designing-an-8-bit-parity-generator-and-checker-circuits/ https://www.engineersgarage.com/vhdl-tutorial-12-designing-an-8-bit-parity-generator-and-checker-circuits/#respond Tue, 20 Apr 2021 17:30:13 +0000 https://www.engineersgarage.com/?p=62249 Note: it’s recommended to follow this VHDL tutorial series in order, starting with the first tutorial. In the previous tutorial VHDL tutorial – 11, we learned how to design half and full-subtractor circuits by using the VHDL. In this tutorial, we will: Write a VHDL program to build an 8-bit parity generator and checker circuits Verify…

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]]> https://www.engineersgarage.com/vhdl-tutorial-12-designing-an-8-bit-parity-generator-and-checker-circuits/feed/ 0 VHDL Tutorial – 11: Designing half and full-subtractor circuits https://www.engineersgarage.com/vhdl-tutorial-11-designing-half-and-full-subtractor-circuits/ https://www.engineersgarage.com/vhdl-tutorial-11-designing-half-and-full-subtractor-circuits/#respond Tue, 20 Apr 2021 17:04:13 +0000 https://www.engineersgarage.com/?p=62239 Note: it’s recommended to follow this VHDL tutorial series in order, starting with the first tutorial. In previous tutorial VHDL tutorial – 10, we had designed half and full-adder circuits using VHDL. In this tutorial, we will: Write a VHDL program to build half and full-subtractor circuits Verify the output waveform of program (digital circuit) with…

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