How to design half and full-adder circuits in Verilog

Note: it’s recommended to follow this VHDL tutorial series in order, starting with the first tutorial. Follow the full series here.

In the previous tutorial, VHDL Tutorial – 9, we learned how to build digital circuits using Boolean equations.

In this tutorial, we’ll:

Write a Verilog program that builds half and full-adder circuits
Verify the output waveform of the program (digital circuit) with the truth table for the half and full-adder circuits.

Half-adder circuit

Truth table

Let’s write the VHDL program, compile and simulate it, and get the output in a waveform. We’ll also verify the output waveforms with the given truth table.

First, it’s important to review the step-by-step procedure provided in VHDL Tutorial – 3. In that tutorial, we learn how to design a project, edit and compile a program, create a waveform file, simulate the program, and generate the final output waveforms.

VHDL program

Gate-level modeling:

module half_adder(a,b,sum,cry);
input a,b;
output sum,cry;
xor(sum,a,b);
and(cry,a,b);
endmodule

Dataflow modeling:

module half_adder(a,b,sum,cry);
input a,b;
output sum,cry;
assign sum = a ^ b;
assign cry = a & b;
endmodule

Behavior modeling:

module half_adder(a,b,sum,cry);
input a,b;
output sum,cry;
always @(a, b)
   begin
      cry = a & b;
       sum = a ^ b;
   end
endmodule

Next, compile the above program, creating a waveform file with all of the necessary inputs and outputs that are listed, and simulate the project.

Here are the results…

Waveform simulation

Verify that the ‘sum’ and ‘cry’ output waveforms against the given truth table. For the ‘a=1’ and ‘b=0’ inputs, the outputs are ‘sum=1’ and ‘cry=0,’ as highlighted in the above figure.

Now let’s move on to the full-adder circuit design.

Full-adder circuit

Verilog program

Gate-level modeling:

module full_adder(a,b,cin,sum,carry);
input a,b,cin;
output sum,carry;
wire w1,w2,w3,w4;

xor(w1,a,b);
xor(sum,w1,cin); //Sum output
and(w2,a,b);
and(w3,b,cin);
and(w4,cin,a);

or(carry,w2,w3,w4);
endmodule

Dataflow modellng:

module full_adder(a,b,cin,sum,carry);
input a,b,cin;
output sum,carry;
assign sum = a ^ b ^ cin;
assign carry = (a & b) | (b & cin) | (cin & a) ;
endmodule

Next, let’s explore the same program using a different style called structural modeling, where the complete program is divided into different modules.. This style hasn’t been required in the previous tutorials.

For this program, we’ll first create a module for a half-adder and then use it twice. This is called module instantiation. In Verilog, one complete module can be instantiated inside another program, which is a fundamental feature of its programming.

Structural modeling is useful for building large and complex Verilog programs because it allows a complex design to be divided into smaller, more manageable modules. These modules are then instantiated wherever needed in the main program.

//////////// Verilog module of half adder ///////////////

module half_adr(a,b,sum,cy);
input a,b;
output sum,cy;
xor(sum,a,b);
and(cy,a,b);
endmodule

////// Verilog main program of full adder /////////////

module full_adder(a,b,cin,sum,carry);
input a,b,cin;
output sum,carry;
wire w1,w2,w3;
half_adr HA1(a,b,w1,w2); // module instantiation
half_adr HA2(w1,cin,sum,w3);
or(carry,w2,w3);
endmodule

Simulation waveform

Remember to compare the outputs, ‘sum’ and ‘carry’ with the given truth table. As shown in the above figure, one is highlighted as ‘a=1,’ ‘b=1,’ and ‘cin=0,’ with the outputs of ‘sum=0’ and ‘carry=1.’

In next tutorial, we’ll learn how to design half and full-subtractor circuits using Verilog.