Master Verilog Programming: Explore digital circuit models

In the previous tutorial, we covered the fundamentals of Verilog, VLSI design flow, and various Verilog modeling styles, including modules and data types. Now, it’s time to dive into the Verilog programming.

In this tutorial, we’ll present basic Verilog programs for popular digital circuits. Before we begin, it’s worth reviewing the prerequisites for Verilog programming, which is in the introduction to digital electronics and digital circuit design. It’s important to ensure adequate knowledge of Boolean algebra, logic gates, combinational, sequential logic circuits, etc. So, be sure to refresh your digital electronics fundamentals.

Below, we explore the Verilog program for a given digital circuit using two to three modeling styles. This approach will help you gain a comprehensive understanding of how to write Verilog programs using various modeling techniques.

The half-adder

Gate level modeling:

module half_adder(a,b,s,c);
input a,b;
output s,c;
xor(s,a,b);
and(c,a,b);
endmodule

Dataflow modeling:

module half_adder(a,b,s,c);
input a,b;
output s,c;
assign s = a ^ b;
assign c = a & b;
endmodule

Behavior modeling:

module half_adder(a,b,s,c);
input a,b;
output s,c;
always @(a, b)
   begin
                c = a & b;
               s = a ^ b;
   end
endmodule

D-Morgan’s theorems

Gate-level modeling:

module d_morgan(a,b,op1,op2,op3,op4);
input a,b;
output op1,op2,op3,op4;
wire a_bar,b_bar;
not(a_bar,a);
not(b_bar,b);
nand(op1,a,b);
or(op2,a_bar,b_bar);
nor(op3,a,b);
and(op4,a_bar,b_bar);
endmodule

Dataflow modeling:

module d_morgan(a,b,op1,op2,op3,op4);
input a,b;
output op1,op2,op3,op4;

assign op1 = ~(a & b);
assign op2 = ~a | ~b;
assign op3 = ~(a | b);
assign op4 = ~a & ~b;
endmodule

Behavior modeling:

module d_morgan(a,b,op1,op2,op3,op4);
input a,b;
output op1,op2,op3,op4;
always @(a, b)
begin
op1 = ~(a & b);
op2 = ~a | ~b;
op3 = ~(a | b);
op4 = ~a & ~b;
end
endmodule

The parity generator

Gate-level modeling:

module parity(p,d);
output p;
input [3:0] d;
wire t1,t2;
xor(t1,d[0],d[1]);
xor(t2,d[2],t1);
xor(p,d[3],t2);
endmodule

Dataflow modeling:

module parity(p,d);
output p;
input [3:0] d;
wire t1,t2;
assign t1 = d[0] ^ d[1];
assign t2 = d[2] ^ t1;
assign p = d[3] ^ t2;
endmodule

Behavioral modeling:

module parity(p,d);
output p;
input [3:0] d;
wire t1,t2;
always @(d)
begin
t1 = d[0] ^ d[1];
t2 = d[2] ^ t1;
p = d[3] ^ t2;

end
endmodule

The 2 to 4 decoder

Gate-level modeling:

module decoder_2to4(a0,a1,d0,d1,d2,d3 );
input a0,a1;
output d0,d1,d2,d3;
wire a0_bar,a1_bar;
not(a0_bar,a0);
not(a1_bar,a1);
and(d0,a0_bar,a1_bar)
and(d1,a0,a1_bar)
and(d2,a0_bar,a1),
and(d3,a0,a1);
endmodule

Dataflow modeling:

module decoder_2to4(a0,a1,d0,d1,d2,d3 );
input a0,a1;
output d0,d1,d2,d3;
assign d0 = ~a0 & ~a1;
assign d1 = a0 & ~a1;
assign d2 = ~a0 & a1;
assign d3 = a0 & a1;
endmodule

Behavioral modeling:

module decoder_2to4(a0,a1,d0,d1,d2,d3 );
input a0,a1;
output d0,d1,d2,d3;
always @(a0,a1)
begin
d0 = ~a0 & ~a1;
d1 = a0 & ~a1;
d2 = ~a0 & a1;
d3 = a0 & a1;
end
endmodule

The SR flip flop

Dataflow modeling:

module srff_gate(q, qbar, s, r, clk);
input s,r,clk;
output q, qbar;
wire nand1_out;
wire nand2_out;
nand (nand1_out,clk,s);
nand (nand2_out,clk,r);
nand (q,nand1_out,qbar);
nand (qbar,nand2_out,q);
endmodule

Behavioral modeling:

module srff_behave(s,r,clk, q, qbar);
input s,r,clk;
output reg q, qbar;
always@(posedge clk)
begin

if(s == 1)
begin
q = 1;
qbar = 0;
end
else if(r == 1)
begin
q = 0;
qbar =1;
end
else if(s == 0 & r == 0)
begin
q <= q;
qbar <= qbar;
end
end
endmodule

After reviewing these programs, you should be familiar with Verilog programming and its different modeling styles. In the next tutorial, we’ll begin exploring the simulation and verification of Verilog programs for digital circuits.