How to design a digital circuit for a Boolean equation using Verilog

In the previous Verilog tutorial, we learned how to build various logic gates — such as AND, OR, NOR, and NOT — using only the NOR gates in Verilog. As such, we demonstrated that NOR is a universal gate.

(If you haven’t been following this Verilog tutorial series in order, we recommend reviewing the previous tutorials before proceeding with this one. View the full VHDL tutorial series here.)

In this tutorial, we’ll:

Write a Verilog program to construct a digital circuit from a given Boolean equation.
Verify the program’s output waveform (digital circuit) against the truth table of the Boolean equation.

First, let’s review the Boolean equation AB + AC’ + BC.

Digital circuit

Truth table

Now, let’s write a Verilog program, compile and simulate it, and obtain the output in the form of a waveform. Afterward, we’ll verify that the output waveforms match the given truth table.

(Please follow the step-by-step procedure outlined in Verilog Tutorial 3 to create a project, edit and compile the program, create a waveform file, simulate the program, and generate output waveforms.)

Verilog program

Gate-level modeling:

module bol_equ(a,b,c,y);
input a,b,c;
wire t1,t2,t3,c_not;
output y;
    and(t1, a, b);
    and (t2, b, c);
    not (c_not, c);
    and (t3, a, c_not);
    or(y, t1, t2, t3);
endmodule

Dataflow modeling:

module bol_equ(a,b,c,y);
input a,b,c;
wire t1,t2,t3;
output y;
assign t1 = a & b;
assign t2 = a & ~c;
assign t3 = b & c;
assign y = t1 | t2 | t3;
endmodule

Next, compile the above program, creating a waveform file with all of the necessary inputs and outputs that are listed, and simulate the project.

Simulation waveform

You can verify the output “y” by comparing it with the given truth table. It should be observed that the output matches the truth table.

Now, let’s consider another Boolean equation: A + B’C + A’C + BC’

Digital circuit

Truth table

Verilog program

Gate-level modeling:

module boolean_equ (a, b, c, y)
input a, b, c;
output y;
wire t1, t2, t3, t4, t5, a_not, b_not, c_not;
not(a_not, a);
not(b_not, b);
not(c_not, c);
and(t1, b_not, c);
or(t4, a, t1);
and(t2, a_not, c);
and(t3, b, c_not);
or(t5, t2, t3);
or(y, t4, t5);
endmodule

Dataflow modeling:

module boolean_equ (a, b, c, y)
input a, b, c;
output y;
   wire t1, t2, t3, t4, t5;
    assign t1 = (~b & c);
           assign t2 = (~a & c);
    assign t3 = (b & ~c);
    assign t4 = (a | t1);
    assign t5 = (t2 | t3);
    assign y = (t4 | t5);
endmodule