How to use NOR as the universal gate in Verilog

In the previous Verilog tutorial, we learned how to implement various logic gates, including AND, OR, NOR, and NOT, using only NAND gates in Verilog, demonstrating that NAND is a universal gate.

(If you haven’t been following this Verilog tutorial series in order, we recommend reviewing the previous tutorials before proceeding with this one. View the full VHDL tutorial series here.)

In this tutorial, we’ll:

Write a Verilog program to construct all basic logic gates (AND, OR, NOT, XOR, NOR, etc.) using only NOR gates.
Verify the output waveform of the program (digital circuit) against the truth tables of these gates.

Digital circuit

Truth table

Now, let’s write a Verilog program, compile and simulate it, and obtain the output in the form of a waveform. Afterward, we’ll verify that the output waveforms match the given truth table.

(Please follow the step-by-step procedure outlined in Verilog Tutorial 3 to create a project, edit and compile the program, create a waveform file, simulate the program, and generate output waveforms.)

Verilog program

Gate-level modeling:

module nor_uni_gate(a,b,y_not,y_and,y_or,y_xor,y_xnor,y_nor);
input a, b;
output y_not,y_and,y_or,y_xor,y_xnor,y_nor;
wire t1,t2,t3,t4,t5,a_not,b_not;
nor(y_not,a,a);
nor(t1,a,b);
nor(y_and,t1,t1);
nor(a_not,a,a);
nor(b_not,b,b);
nor(y_or,a_not,b_not);
nor(t2,a_not,b_not);
nor(y_nor,t2,t2);
nor(t3,a_not,b);
nor(t4,a,b_not);
nor(y_xor,t3,t4);
nor(t5,t3,t4);
nor(y_xnor,t5,t5);
endmodule

Dataflow modeling:

module nor_uni_gate(a,b,y_not,y_and,y_or,y_xor,y_xnor,y_nor);
input a, b;
output y_not,y_and,y_or,y_xor,y_xnor;
wire t1,t2,t3,t4,t5,t6,t7;
assign y_not = ~(a | a);
assign t1 = ~(a | b);
assign y_or = ~(t1 | t1);
assign t2 = ~ (a | a);
assign t3 = ~ (b | b);
assign y_and = ~(t2 | t3);
assign t4 = ~(~a | b);
assign t5 = ~(a | ~b);
assign y_xor = ~(t4 | t5);
assign t6 = ~(t4 | t5);
assign y_xnor = ~(t6 | t6);
assign t7 = ~(t2 & t3);
assign y_nor = ~(t7 & t7);
endmodule

Next, compile the above program, creating a waveform file with all of the necessary inputs and outputs that are listed, and simulate the project.

Simulation waveform

From these output waveforms, we can clearly see that the outputs of different gate circuits built using only NOR gates match the expected outputs of each respective gate.

This confirms that all basic logic gates can be designed using only NOR gates, proving that the NOR gate is a universal gate.

In the next tutorial, we will design a digital circuit based on a given Boolean equation in Verilog.