How to design, simulate, and verify all digital gates in Verilog

In previous Verilog tutorials (especially Tutorial 3), we learned how to design, simulate, and verify digital circuits using Altera’s MAX+II VHDL/Verilog simulator software. (If you haven’t been following this series sequentially, be sure to review the previous tutorials before proceeding.)

In this tutorial, we’ll:

Write a Verilog program to build various digital logic gates.
Simulate the program to design the digital circuits for these gates.
Verify the output waveforms of the circuits and compare them with the truth tables of the corresponding logic gates.

Let’s begin with the digital circuit for which we will write a Verilog program.

Circuit diagram

Truth table

The truth table for above circuit:

Now, let’s write a Verilog program. We’ll compile and simulate it, viewing the output as waveforms. Lastly, we’ll verify that the output waveforms match the expected truth table.

(Please refer to the step-by-step procedure outlined in the previous tutorial, which covers how to edit and compile the program, create a waveform file, simulate the program, and generate output waveforms.)

Verilog program

Gate-level modeling:

module all_gates(y_and,y_or,y_xor,y_nand,y_nor,y_xnor,y_not,a, b);
output y_and,y_or,y_xor,y_nand,y_nor,y_xnor,y_not;
input a,b;
and(y_and, a, b);
or(y_or, a, b);
xor(y_xor, a, b);
nand(y_nand, a, b);
nor(y_nor, a, b);
xnor(y_xnor, a, b);
not(y_not,a);
endmodule

Dataflow modeling:

module all_gate(a,b,y_and,y_or,y_nand,y_nor,y_not, y_xor,y_xnor);
input a,b;
output y_and,y_or,y_nand,y_nor,y_not,y_xor,y_xnor;
assign y_and = a & b;
assign y_or = a | b;
assign y_not = ~a;
assign y_nand = ~(a & b);
assign y_nor = ~(a | b);
assign y_xor = a ^ b;
assign y_xnor = ~(a ^ b);
endmodule

Next, compile the program. Create a waveform file with all inputs and outputs listed, and simulate the project to obtain the below result.

Note: Make sure to write the program using only one modeling style at a time, and then compile it. You can modify the program using a different modeling style and then recompile it. You can also experiment with a third modeling style, such as behavioral modeling (not provided here), and verify the results.

Simulation waveform

Now, verify these output waveforms against the truth table for the logic gates. For instance, the highlighted case shows inputs “a = 1″ and “b = 1.” You can also verify the other three cases.

This is how you can create a simple logic gate circuit in Verilog and validate its output using the truth table.

In the next tutorial, we’ll explore A-O-I implementation of NAND, NOR, XOR, and XNOR gates. A-O-I implementation involves building digital circuits using only AND, OR, and NOT gates.