How to design and verify D’Morgan’s Theorem in Verilog-Part 6

In tutorial 5 of this series, we built NAND, NOR, XOR, and XNOR gates using AND, OR, and NOT gates in Verilog. (If you haven’t been following along, we highly recommend reviewing the previous tutorials before proceeding with this one. The first tutorial starts here.)

In this tutorial, we’ll:

Write a Verilog program to design a digital circuit demonstrating De Morgan’s Theorems.
Verify the program’s output waveform (digital circuit) against the truth table for De Morgan’s Theorems.

Statements of De Morgan’s Theorems

Theorem 1. The complement of the sum of two or more variables is equal to the product of the complements of the variables. This means:

Theorem 2. The complement of the product of two or more variables is equal to the sum of the complement of the variables. This means:

Let’s begin with the digital circuit for which we’ll write the Verilog program.

Digital circuit

Here are the truth tables for the above circuit.

Next, let’s write the Verilog program, compile and simulate it, and generate the output as a waveform. Then, we’ll verify the output waveforms against the given truth table.

(Please refer to the step-by-step procedure in Verilog Tutorial 3 to create a project, edit and compile the program, create a waveform file, simulate the program, and generate output waveforms.)

Verilog program

Gate level modeling:

module d_morgan(a,b, or_not_op,not_and_op,and_not_op, not_or_op);
input a,b;
output or_not_op,not_and_op,and_not_op, not_or_op;
wire a_bar,b_bar;
     not(a_bar,a);
     not(b_bar,b);
     nand(and_not_op,a,b);
     or(not_or_op,a_bar,b_bar);
     nor(or_not_op,a,b);
     and(not_and_op,a_bar,b_bar);
endmodule

Dataflow modeling:

module d_morgan(a,b,or_not_op,not_and_op,and_not_op, not_or_op);
input a,b;
output or_not_op,not_and_op,and_not_op, not_or_op;
     assign and_not_op = ~(a & b);
     assign not_or_op = ~a | ~b;
     assign or_not_op = ~(a | b);
     assign not_and_op = ~a & ~b;
endmodule

Behavior modeling:

module d_morgan(a,b, or_not_op,not_and_op,and_not_op, not_or_op);
input a,b;
output or_not_op,not_and_op,and_not_op, not_or_op;
always @(a, b)
   begin
and_not_op = ~(a & b);
     not_or_op = ~a | ~b;
      or_not_op = ~(a | b);
      not_and_op = ~a & ~b;
   end
endmodule

(To learn more about Verilog programs, be sure to review Verilog tutorial 1 and Verilog tutorial 2 of these series.)

Now, compile the above program by creating a waveform file with all of the inputs and outputs listed. Then, simulate the project, and you should get the following result.

Simulation waveform

Note, you can write the program using one modeling style at a time and then compile it. Afterward, modify the program to use a different modeling style and compile it again.

From the output waveforms, we can observe that the result of OR followed by NOT is the same as NOT followed by AND. This is highlighted in the figure. Similarly, the other two outputs are also identical.

This confirms the validity of De Morgan’s theorems.

In the next tutorial, we’ll demonstrate how a NAND gate can function as a universal gate by designing AND, OR, NOT, XOR, and XNOR gates using only NAND gates.