{"id":83126,"date":"2025-06-08T23:50:16","date_gmt":"2025-06-09T03:50:16","guid":{"rendered":"https:\/\/www.engineersgarage.com\/?p=83126"},"modified":"2025-06-10T17:41:22","modified_gmt":"2025-06-10T21:41:22","slug":"verilog-tutorial-14-how-to-design-a-1x8-demultiplexer-and-an-8x1-multiplexer-in-verilog","status":"publish","type":"post","link":"https:\/\/www.engineersgarage.com\/verilog-tutorial-14-how-to-design-a-1x8-demultiplexer-and-an-8x1-multiplexer-in-verilog\/","title":{"rendered":"Verilog Tutorial 14: How to design a 1\u00d78 demultiplexer and an 8\u00d71 multiplexer in Verilog"},"content":{"rendered":"

Note: it\u2019s recommended to follow this VHDL tutorial series in order, starting with the\u00a0<\/em>first tutorial<\/em><\/a><\/strong>. Follow the full series\u00a0here<\/a>.<\/strong><\/em><\/p>\n

In the previous\u00a0Verilog Tutorial \u2013 13<\/strong><\/a>, we learned how to design\u00a0a 3\u00d78 decoder and an 8\u00d73 encoder in VHDL.<\/p>\n

In this tutorial, we\u2019ll:<\/p>\n

    \n
  1. Write a Verilog program to build circuits for a 1\u00d78 demultiplexer and an 8\u00d71 multiplexer<\/li>\n
  2. Verify the output waveform of program (digital circuit) with truth table of these multiplexer and demultiplexer circuits<\/li>\n<\/ol>\n

    The 1\u00d78 Demultiplexer circuit<\/strong><\/h3>\n

    \"\"<\/a><\/p>\n

    Truth table<\/h3>\n

    \"\"<\/a><\/p>\n

    Next, let\u2019s write the\u00a0Verilog\u00a0program, compile and simulate it, and get the output in a waveform. We\u2019ll also verify the output waveforms with the given truth table.<\/p>\n

    First, it\u2019s important to review the step-by-step procedure provided in\u00a0VHDL Tutorial \u2013 3<\/a><\/strong>. In that tutorial, we learn how to design a project, edit and compile a program, create a waveform file, simulate the program, and generate the final output waveforms.<\/span><\/p>\n

    Verilog program<\/span><\/strong><\/h3>\n

    Gate-level modeling:<\/strong><\/p>\n

    module demux18(o1,o2,o3,o4,o5,o6,o7,o8,D,s0,s1,s2);<\/strong><\/span>
    \n\u00a0input\u00a0 i,s0,s1,s2;<\/strong><\/span>
    \n\u00a0output o1,o2,o3,o4,o5,o6,o7,o8;<\/strong><\/span>
    \n\u00a0wire not_s0,not_s1,not_s2;<\/strong><\/span>
    \nnot(not_s0,s0);<\/strong><\/span>
    \nnot(not_s1,s1);<\/strong><\/span>
    \nnot(not_s2,s2);<\/strong><\/span>
    \nand(o1,not_s0,not_s1,not_s2,i);<\/strong><\/span>
    \nand(o2,s0,not_s1,not_s2,i);<\/strong><\/span>
    \nand(o3,not_s0,s1,not_s2,i);<\/strong><\/span>
    \nand(o4,s0,s1,not_s2,i);<\/strong><\/span>
    \nand(o5,not_s0,not_s1,s2,i);<\/strong><\/span>
    \nand(o6,s0,not_s1,s2,i);<\/strong><\/span>
    \nand(o7,not_s0,s1,s2,i);<\/strong><\/span>
    \nand(o8,s0,s1,s2,i);<\/strong><\/span>
    \nendmodule<\/strong><\/span><\/p>\n

    Dataflow modeling:<\/strong><\/p>\n

    module demux18(o1,o2,o3,o4,o5,o6,o7,o8,D,s0,s1,s2);<\/strong><\/span>
    \n\u00a0input\u00a0 i,s0,s1,s2;<\/strong><\/span>
    \n\u00a0output o1,o2,o3,o4,o5,o6,o7,o8;<\/strong><\/span><\/p>\n

    assign o1 = ~s0 & ~s1 & ~s2 & i;<\/strong><\/span>
    \nassign o2 = s0 & ~s1 & ~s2 & i;<\/strong><\/span>
    \nassign o3 = ~s0 & s1 & ~s2 & i;
    \n<\/strong><\/span>assign o4 = s0 & s1 & ~s2 & i;<\/strong><\/span>
    \nassign o5 = ~s0 & ~s1 & s2 & i;<\/strong><\/span>
    \nassign o6= s0 & ~s1 & s2 & i;<\/strong><\/span>
    \nassign o7 = ~s0 & s1 & s2 & i;<\/strong><\/span>
    \nassign o8 = s0 & s1 & s2 & i;<\/strong><\/span>
    \nendmodule<\/strong><\/span><\/p>\n

    Now, compile the above program, creating a waveform file with all of the necessary inputs and outputs that are listed, and simulate the project.\u00a0<\/span><\/p>\n

    Here are the results\u2026<\/span><\/p>\n

    Waveform simulation<\/h3>\n

    \"\"<\/a><\/p>\n

    As shown above, the 8\u00d71 multiplexer can be understood by examining the select lines and corresponding outputs. When the select lines (S2, S1, S0) are set to ‘001,’ input I\u2080 is routed to the output, resulting in ‘O\u2081 = 0.’<\/p>\n

    Similarly, when the select lines are ‘101,’ input I\u2085 is selected, and the output becomes ‘O\u2085 = 1.’ You can also verify other combinations of the select lines by observing how each input is connected to its corresponding output.<\/p>\n

    Next, let’s build the 8\u00d71 multiplexer circuit.\u00a0<\/u><\/strong><\/p>\n

    The 8×1 multiplexer circuit<\/strong><\/h3>\n

    \"\"<\/a>Verilog program:<\/strong><\/h3>\n

    Gate-level modeling:<\/strong><\/p>\n

    module mux81(o, D0, D1, D2, D3, D4, D5, D6, D7, S0, S1, S2);<\/strong><\/span>
    \n\u00a0 input\u00a0 D0, D1, D2, D3, D4, D5, D6, D7, S0, S1, S2;<\/strong><\/span>
    \n\u00a0 output o;<\/strong><\/span>
    \n\u00a0 wire o1,o2,o3,o4,o5,o6,o7,o8,x,y,z;<\/strong><\/span>
    \nnot(x,S0);<\/strong><\/span>
    \nnot(y,S1);<\/strong><\/span>
    \nnot(z,S2);<\/strong><\/span>
    \nand(o1,x,y,z,D0);<\/strong><\/span>
    \nand(o2,S0,y,z,D1);<\/strong><\/span>
    \nand(o3,x,S1,z,D2);<\/strong><\/span>
    \nand(o4,S0,S1,z,D3);<\/strong><\/span>
    \nand(o5,x,y,S2,D4);<\/strong><\/span>
    \nand(o6,S0,y,S2,D5);<\/strong><\/span>
    \nand(o7,x,S1,S2,D6);<\/strong><\/span>
    \nand(o8,S0,S1,S2,D7);<\/strong><\/span>
    \nor(o,o1,o2,o3,o4,o5,o6,o7,o8);<\/strong><\/span>
    \nendmodule<\/strong><\/span><\/p>\n

    Dataflow modeling:<\/strong><\/p>\n

    module mux81(o, D0, D1, D2, D3, D4, D5, D6, D7, S0, S1, S2);<\/strong><\/span>
    \n\u00a0 input\u00a0 D0, D1, D2, D3, D4, D5, D6, D7, S0, S1, S2;<\/strong><\/span>
    \n\u00a0 output o;<\/strong><\/span>
    \n\u00a0 wire o1,o2,o3,o4,o5,o6,o7,o8;<\/strong><\/span>
    \nassign o1 = ~S0 & ~S1 & ~S2 & D0;<\/strong><\/span>
    \nassign o2 = S0 & ~S1 & ~S2 & D1;<\/strong><\/span>
    \nassign o3 = ~S0 & S1 & ~S2 & D2;<\/strong><\/span>
    \nassign o4 = S0 & S1 & ~S2 & D3;<\/strong><\/span>
    \nassign o5 = ~S0 & ~S1 & S2 & D4;<\/strong><\/span>
    \nassign o6 = S0 & ~S1 & S2 & D5;<\/strong><\/span>
    \nassign o7 = ~S0 & S1 & S2 & D6;<\/strong><\/span>
    \nassign o8 = S0 & S1 & S2 & D7;<\/strong><\/span>
    \nassign o = o1 | o2 | o3 | o4 | o5 | o6 | o7 | o8;<\/strong><\/span>
    \nendmodule<\/strong><\/span><\/p>\n

    Simulation waveform<\/strong><\/h3>\n

    \"\"<\/a><\/p>\n

    As shown in the figure, when the select lines (S2, S1, S0) are set to \u201c011\u201d and \u201c100,\u201d the corresponding inputs d\u2083 = 1 and d\u2084 = 1 are passed to the output, resulting in o = 1. You can verify additional select line combinations using the truth table.<\/p>\n

    In the next tutorial, we’ll design the RS flip-flop and the clocked RS latch.<\/em><\/p>\n

    \n","protected":false},"excerpt":{"rendered":"

    Note: it\u2019s recommended to follow this VHDL tutorial series in order, starting with the\u00a0first tutorial. Follow the full series\u00a0here. In the previous\u00a0Verilog Tutorial \u2013 13, we learned how to design\u00a0a 3\u00d78 decoder and an 8\u00d73 encoder in VHDL. In this tutorial, we\u2019ll: Write a Verilog program to build circuits for a 1\u00d78 demultiplexer and an…<\/p>\n","protected":false},"author":64,"featured_media":83133,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_genesis_hide_title":false,"_genesis_hide_breadcrumbs":false,"_genesis_hide_singular_image":false,"_genesis_hide_footer_widgets":false,"_genesis_custom_body_class":"","_genesis_custom_post_class":"","_genesis_layout":"","footnotes":""},"categories":[9,1],"tags":[4692,4693,4288,4534],"class_list":{"2":"type-post","13":"entry","14":"has-post-thumbnail"},"acf":[],"yoast_head":"\ndesign-a-1x8-demultiplexer-and-an-8x1-multiplexer-in-verilog<\/title>\n<meta name=\"description\" content=\"Follow this Verilog tutorial to simulate circuits for multiplexers and demultiplexers and verify their outputs.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, 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